prikaz prve stranice dokumenta Harverdska implementacija floating-point jedinice za hack računalo
  Download
PDF 8.78 MB
undergraduate thesis
Harverdska implementacija floating-point jedinice za hack računalo
2024. urn:nbn:hr:126:578305
Orlić, Robert
Josip Juraj Strossmayer University of Osijek
School of Applied Mathematics and Informatics

Cite this document

Orlić, R. (2024). Harverdska implementacija floating-point jedinice za hack računalo (Undergraduate thesis). Osijek: Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics. Retrieved from https://urn.nsk.hr/urn:nbn:hr:126:578305

Orlić, Robert. "Harverdska implementacija floating-point jedinice za hack računalo." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics, 2024. https://urn.nsk.hr/urn:nbn:hr:126:578305

Orlić, Robert. "Harverdska implementacija floating-point jedinice za hack računalo." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics, 2024. https://urn.nsk.hr/urn:nbn:hr:126:578305

Orlić, R. (2024). 'Harverdska implementacija floating-point jedinice za hack računalo', Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics, accessed 10 November 2024, https://urn.nsk.hr/urn:nbn:hr:126:578305

Orlić R. Harverdska implementacija floating-point jedinice za hack računalo [Undergraduate thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics; 2024 [cited 2024 November 10] Available at: https://urn.nsk.hr/urn:nbn:hr:126:578305

R. Orlić, "Harverdska implementacija floating-point jedinice za hack računalo", Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, School of Applied Mathematics and Informatics, Osijek, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:126:578305

Please login to the repository to save this object to your list.
Metadata
TitleHarverdska implementacija floating-point jedinice za hack računalo
Title (english)Hardware Implementation of the Floating-Point Unit for the Hack Computer
AuthorRobert Orlić
MentorDomagoj Matijević (mentor)
GranterJosip Juraj Strossmayer University of Osijek
School of Applied Mathematics and Informatics
Osijek
Defense date and country2024-09-20, Croatia
Scientific / art field,
discipline and subdiscipline		NATURAL SCIENCES
Mathematics
Mathematical Logic and Accounting
Abstract
U ovom radu proći ćemo kroz hardversku implementaciju 16-bitne floating-point jedinice za Hack računalo. Upoznat ćemo se s osnovama HDL-a, detaljno opisati hardversku implementaciju floating-point jedinice te se naposljetku dotaknuti softverskog dijela implementacije i ukratko ga opisati.
Abstract (english)
In this paper we will go through the hardware implementation of a 16-bit floating-point unit for a Hack computer. We will get to know the basics of HDL, thoroughly describe the hardware implementation of the floating point-unit and eventually say something about the software implementation and describe it briefly.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:126:578305
Study programmeTitle: Bachelor of Mathematics and Computer Science
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) matematike i računarstva (sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) matematike i računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2024-09-26 05:58:53